1. Field of the Invention
The present invention generally relates to a voltage regulator, and more particularly, to a voltage regulator outputting positive and negative voltages with the same offsets.
2. Description of the Prior Art
The era of digital information has arrived which has pushed the development of electronic information processing devices such as computers, wireless devices, personal digital assistants (PDAs), portable multimedia players/recorders, and the like in the recent years. One crucial component to any electronic information processing device is the memory device which has gone under substantial advancement. The performance in speed and reliability along with the size and packaging of these memory devices have greatly improved, and as a result smaller and faster memory devices are continuously being introduced to the market.
In order to reduce power consumption and extend battery life, much of the integrated circuitry such as memory devices used in portable devices is being designed to run at low voltage levels. This reduces the power usage and reduces the heat generated by the circuit components allowing more components to be placed closer to one another. The circuitry and components used in portable computers typically are being designed to operate at voltages levels substantially less than the previous standard of 5V, with 1.0V and lower becoming increasingly common.
Many designs used a technique called “bootstrapping” to generate higher amplitude clock signals to compensate for the increased effective threshold voltages relative to the supply voltage. The bootstrapping technique involves the use of a charge capacitor that charges on every clock pulse and discharges between pulses, adding the discharged voltage to the original input voltage of the bootstrapping circuit so the output could be multiplied to a number of times the original input. Applying a uniform high clock voltage, generated by bootstrapping, leads to energy inefficiency because the greater the current delivered by the clocking voltage, the less efficient the bootstrapping operation. In the latter stages where high voltages are required, this inefficiency was unavoidable. In the initial stages of the charge pump, where as high a voltage is not needed, the clock bootstrapping operation was inefficient.
Different approaches to designing charge pumps were previously disclosed, for example U.S. Pat. No. 6,756,838 “Charge pump based voltage regulator with smart power regulation”, U.S. Pat. No. 5,306,954 “Charge pump with symmetrical +V and −V outputs”, and U.S. Pat. No. 6,717,458 “Method and apparatus for a DC-DC charge pump voltage converter-regulator circuit”. Please refer to FIG. 1, which is a general schematic diagram of a charge pump circuit 10 disclosed in U.S. Pat. No. 5,306,954. An oscillator is used to generate switch signals S1, S2, S3, and S4 to control the operations of the switches. Therefore, each of the capacitors 12, 14, 16, and 18 of the charge pump circuit 10 are charged and discharged repeatedly to pump the voltage levels of the output terminals of the charge pump circuit 10 to +2V and −2V respectively. However, because the voltage offset of the negative terminal of the charge pump circuit 10, i.e. 2V (from GND to −2V), is greater than the offset positive terminal of the charge pump circuit 10, i.e. 1V (from +V to +2V), the capacitance of the capacitor 16 used for storing the negative pump charge is greater than the capacitance of the capacitor 18 used for storing the positive pump charge.
Please refer to FIG. 2, which is a diagram used to illustrate voltage adjustment of prior art voltage regulators. The two input terminals of the prior voltage regulator respectively are coupled to a first voltage source VDD and a second voltage source VSS. The first voltage source VDD provides a positive voltage, and the second voltage source VSS is connected to the ground. In general, the voltage regulator comprises a first pump circuit and a second pump circuit to pump up or pump down the voltage level the output terminals of the voltage regulator by charging and discharging. The first pump circuit pumps up the output voltage from VDD to VPP, the second pump circuit pumps down the output voltage from VSS to VBB. The difference between VPP and VBB is equal to VH, i.e. |VPP−VBB|=VH, and the difference between VSS and VBB is equal to VPP, i.e. |VSS−VBB|=VPP. Therefore, the offset of the output voltage of the first pump circuit ΔV1 is greater than the offset of the output voltage of the second pump circuit ΔV2. In such structure, the number of the capacitors of the first pump circuit is less than the number of the capacitors of the second pump circuit. Hence, the energy transforming efficiency of the second pump circuit is less the energy transforming efficiency of the first pump circuit. Moreover, because the voltage gap ΔV2 maintained by the second pump circuit is greater than the voltage gap ΔV1 maintained by the first pump circuit, the capacitance of the capacitor of the second pump circuit is greater than the capacitance of the capacitor of the first pump circuit. Hence, the area of the capacitor of the second pump circuit is greater than the capacitance of the capacitor of the first pump circuit. Briefly summarized, the second pump circuit of the voltage regulators according to the prior art have disadvantages as follows: having poor energy transforming efficiency and an undue size of its capacitor.